It has become more important in recent years that processor-based systems (such as workstations and servers) feature power-down or sleep (low-power) modes, to save the power that would otherwise be driving the system even when at least some subsystems may not be in use. For instance, it is economical to power down a local device control system in a computer system that is not actively in use.
However, in certain systems it may be undesirable to enter a low-power mode for the entire device control system, since some of the devices may require continued clocking to maintain the integrity of their data or state. A recently developed example is double-data rate (DDR) memory modules such as DIMMs (double in-line memory modules), which can benefit by continued clock generation even when their associated circuits in the computer system (such as the memory controller and other local device control circuitry) are in a low-power mode.
It is therefore desirable to arrive at a system that allows such devices as DDR DIMMs to continue to receive a clock signal and remain in an active state even when the circuitry that drives such devices is itself in a powered-down or sleep mode.
In order to continue the clocking of a device such as a DDR DIMM when a portion of a computer system enters an energy-saving mode, wherein the usual core clock signal is inhibited, a system according one embodiment of the invention includes a clock bypass circuit providing bypass clock signals. The computer system may typically include a phase-locked loop (PLL) circuit that receives the core clock as input, and outputs a phase-locked core clock, which is then provided to a clock tree for distribution to components of the computer system.
To implement an energy saving (low-power) mode, a clock gate is provided at the input end of the clock tree, and the gate blocks passage of the (phase-locked) core clock when the low-power mode is desired.
The bypass clock signals do not, however, pass through the clock gate, and instead, are provided as input to the memory modules or other devices that are to continue operating even during low-power mode. In this way, refresh or reset operations are avoided for such memory modules or other devices, with their resultant refresh time periods and possible signal or data corruption during a reset procedure.
In one embodiment of the invention, the bypass clock signals are passed through a skew compensation circuit, which is clocked by a double-frequency (2xc3x97) clock from the PLL circuit. The skew compensation circuit realigns the bypass clock signal with the 2xc3x97 clock signal, if any skew has taken place. In addition, control signals are similarly aligned with the 2xc3x97 clock signal by another circuit, so that the bypass clock signals and the control signals are substantially coordinated.
For DDR DIMMs, the bypass clock signal is additionally converted into a differential clock signal by a the skew compensation circuit, for more reliable, noise-free clock signals.
Since conventional PLL circuits use feedback clock signals, the bypass clock signals can be derived from the PLL feedback clock signals. A delay-matching circuit may be used in the feedback clock circuit to compensate for path delays introduced by the clock tree circuit.